Temperature-Controlled Storage Module

ABSTRACT

A temperature-controlled storage module is disclosed. In one embodiment, a storage module is provided comprising a memory, a temperature sensor, a thermoelectric cooler, and a controller. The controller compares a temperature reading from the temperature sensor to a target temperature. If the temperature reading differs from the target temperature, the controller activates the thermoelectric cooler. For example, if the temperature reading is higher than the target temperature, the thermoelectric cooler can be activated to cool the memory. This allows the memory (e.g., NAND die(s)) to operate in a narrow range of temperatures providing better system tradeoffs on memory (e.g., NAND) characteristics.

BACKGROUND

The behavior of memories, such as NAND flash memories, is often verydependent on its operating and storage temperature. In hightemperatures, the endurance is improved due to better annealing, butdata retention is degraded according to the Arrhenius equation. In verylow temperatures, other effects are prominent. Memory designers takethis dependence into consideration to produce a memory that operates ina wide range of temperatures, which provides a compromise between dataretention, endurance, and other memory characteristics. However,operating at wide range of temperatures is a compromise, as certaincharacteristics are better suited for a smaller temperature rangetailored to their specific operations.

Temperature-related issues affect storage modules is other ways as well.For example, increases in read and write performance often requiremultiple memory dies or plane parallelism to achieve the desiredperformance. Current consumption and heat dissipation are two majorfactors that may limit the amount of parallelism in a storage module.Even if there is no limitation on current consumption and the host canguarantee a required housing temperature, there can still be a heatproblem due to the passive heat resistance between the memory dies andthe housing. Moreover, typical host access to the storage module isoften in short, intensive demands for data known as bursts. During thetime of a burst, more demand is placed on the memory, which can increasethe temperature of the memory to levels at or above the maximumoperating temperature rating.

OVERVIEW

Embodiments of the present invention are defined by the claims, andnothing in this section should be taken as a limitation on those claims.

By way of introduction, the below embodiments relate to atemperature-controlled storage module. In one embodiment, a storagemodule is provided comprising a memory, a temperature sensor, athermoelectric cooler, and a controller. The controller compares atemperature reading from the temperature sensor to a target temperature.If the temperature reading differs from the target temperature, thecontroller activates the thermoelectric cooler. For example, if thetemperature reading is higher than the target temperature, thethermoelectric cooler can be activated to cool the memory. This allowsthe memory (e.g., NAND die(s)) to operate in a narrow range oftemperatures providing better system tradeoffs on memory (e.g., NAND)characteristics.

Other embodiments are possible, and each of the embodiments can be usedalone or together in combination. Accordingly, various embodiments willnow be described with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary storage module of anembodiment.

FIG. 2A is a block diagram of a host of an embodiment, where theexemplary storage module of FIG. 1 is embedded in the host.

FIG. 2B is a block diagram of the exemplary storage module of FIG. 1removably connected to a host, where the storage module and host areseparable, removable devices.

FIG. 3 is a flow chart of a method of an embodiment for controlling thetemperature of a storage module.

FIG. 4 is a diagram of a circuit of an embodiment for controlling thetemperature of a storage module.

FIG. 5 is a diagram of a storage module of an embodiment with a singlethermoelectric cooler.

FIG. 6 is a diagram illustrating heat transfer from the storage moduleof FIG. 5.

FIG. 7 is a diagram of a storage module of an embodiment with twothermoelectric coolers.

FIG. 8 is a diagram illustrating heat transfer from the storage moduleof FIG. 7.

FIGS. 9A and 9B are illustrations of an embodiment in which memory diesare cooled prior to a burst period.

FIG. 10 is an illustration of a storage module of another embodiment.

FIG. 11 is an illustration of a prior art thermoelectric cooler.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

Turning to the drawings, FIG. 1 is a diagram of a storage module 100 ofan embodiment. As illustrated in FIG. 1, the storage module 100comprises a controller 110 in communication with one or more memory dies120 having in or on them a temperature sensor 125. As used herein, thephrase “in communication with” could mean directly in communication withor indirectly in communication with through one or more components,which may or may not be shown or described herein. FIG. 1 shows thememory dies 120 as NAND memory dies; however, other memory technologycan be used. Also, the memory 120 can be one-time programmable, few-timeprogrammable, or many-time programmable. The memory 120 can also usesingle-level cell (SLC), multiple-level cell (MLC), triple-level cell(TLC), or other memory technologies, now known or later developed. Also,the memory 120 can be two-dimensional or three-dimensional (e.g., BitCost Memory (BiCS)) and can be a multi-chip package or a single-chippackage.

The storage module 100 in FIG. 1 also comprises a temperature transferdevice, such as a thermoelectric cooler (TEC) 130. (In one embodiment,the controller 110, memory die(s) 130, and TEC 130 are all stacked on asubstrate, and all of those components are housed in an integratedcircuit package 50.) A thermoelectric cooler is a solid-state devicethat uses the Peltier effect to create a heat flux between the junctionof two different types of materials. In general, thermoelectric coolersoperate by the Peltier effect. As shown in FIG. 11, one type of priorart thermoelectric cooler 1100 (other types can be used) has two sides,and when DC current flows through the cooler 1100, it brings heat fromone side of the cooler 1100 to the other side. This results in one sidegetting cooler while the other side gets hotter. The side that getscooler is attached to a cooling plate 1110, and the side that getshotter is attached to a heat sink 1120. The thermoelectric cooler 1100can be made from two unique semi-conductors (one p-type 1130 and onen-type 1140) with different electron densities. The semi-conductors1130, 1140 are placed thermally in parallel to each other andelectrically in series and then joined with thermally-conducting plates1150, 1160 on each side (with insulators 1170, 1180 next to them). Whena voltage is applied to the free ends of the two semiconductors 1130,1140, there is a flow of DC current across the junction of thesemi-conductors 1130, 1140 causing a temperature difference. The sidewith the cooling plate 1110 absorbs heat, which is then moved to theother side with the heat sink 1112.

Because a thermoelectric cooler is a heat pump that transfers heat fromone side of the device to the other with consumption of electricalenergy, a thermoelectric cooler can be used either for cooling(refrigeration) or heating depending on the direction of the current. Aswill be discussed below, in these embodiments, the thermoelectric cooleris used to cool or heat the memory dies 120 in order to keep a desiredtemperature. Because cooling and heating requires extra current from apower supply, such power requirements should be taken intoconsiderations when designing a system for use with the storage module100 to ensure adequate power is being supplied to the storage module100. Due to the power requirements, the storage module 100 may findparticular use where there is no shortage of power, such as in asolid-state drive or in a host device (e.g., a set-top box) withembedded memory. However, these embodiments can also be used withremovable storage devices. For example, the storage module 100 canreceive power from an outside source to power the controller 110 andmemory 120 or can have its own power source (e.g., a battery). Further,as will be described below, there can be additional TECs internal to orexternal to (such as (TEC 2) 150) the storage module 100. The use of thethermoelectric cooler 130 will be discussed in detail below.

As shown in FIG. 2A, the storage module 100 can be embedded in a host210 having a host controller 220. That is, the host 210 embodies thehost controller 220 and the storage module 100, such that the hostcontroller 220 interfaces with the embedded storage module 100 to manageits operations. For example, the storage module 100 can take the form ofan iNAND™ eSD/eMMC embedded flash drive by SanDisk Corporation. The hostcontroller 220 or another component in the host 210 would supply thestorage module 100 with power. The host controller 220 can interfacewith the embedded storage module 100 using a storage interface such aseMMC, UFS, USB, SATA, SAS, SCSI, fiber channel, or PCIe, for example.The host 210 can take any form, such as, but not limited to, a solidstate drive (SSD), a hybrid storage device (having both a hard diskdrive and a solid state drive), a memory caching system, a mobile phone,a tablet computer, a digital media player, a game device, a personaldigital assistant (PDA), a mobile (e.g., notebook, laptop) personalcomputer (PC), or a book reader. As shown in FIG. 2A, the host 210 caninclude optional other functionality modules 230. For example, if thehost 210 is a mobile phone, the other functionality modules 230 caninclude hardware and/or software components to make and place telephonecalls. As another example, if the host 210 has network connectivitycapabilities, the other functionality modules 230 can include a networkinterface. Of course, these are just some examples, and otherimplementations can be used. Also, the host 210 can include othercomponents (e.g., an audio output, input-output ports, etc.) that arenot shown in FIG. 2A to simplify the drawing.

As shown in FIG. 2B, instead of being an embedded device in a host, thestorage module 100 can have physical and electrical connectors thatallow the storage module 100 to be removably connected to a host 240(having a host controller 245) via mating connectors. The hostcontroller 245 or another component in the host 240 could supply thestorage module 100 with power, or power could be provided to the storagemodule 100 from another device. In this embodiment, the storage module100 is a separate device from (and is not embedded in) the host 240. Thestorage module 100 can be, for example, a removable memory device, suchas a Secure Digital (SD) memory card, a microSD memory card, a CompactFlash (CF) memory card, or a universal serial bus (USB) device (with aUSB interface to the host), and the host 240 is a separate device, suchas a mobile phone, a tablet computer, a digital media player, a gamedevice, a personal digital assistant (PDA), a mobile (e.g., notebook,laptop) personal computer (PC), or a book reader, for example.

In FIGS. 2A and 2B, the storage module 100 is in communication with ahost controller 220 or host 240 via storage interface. The storageinterface can take any suitable form, such as, but not limited to, eMMC,UFS, UBS, SATA, SAS, SCSI, fiber channel, or PCIe, for example. Theinterface in the storage module 110 conveys memory management commandsfrom the host controller 220 (FIG. 2A) or host 240 (FIG. 2B) to thecontroller 110, and also conveys memory responses from the controller110 to the host controller 220 (FIG. 2A) or host 240 (FIG. 2B). Also, itshould be noted that when the storage module 110 is embedded in the host210, some or all of the functions described herein as being performed bythe controller 110 in the storage module 100 can instead be performed bythe host controller 220.

Returning to FIG. 1, the controller 110 comprises a host interfacemodule 111, a flash management module 112, a flash interface module 113,a TEC controller 115, and an optional temperature sensor 117. Thecontroller 110 can be implemented in any suitable manner and can be acontroller from SanDisk or from another vendor. For example, thecontroller 110 can take the form of a microprocessor or processor and acomputer-readable medium that stores computer-readable program code(e.g., software or firmware) executable by the (micro)processor, logicgates, switches, an application specific integrated circuit (ASIC), aprogrammable logic controller, and an embedded microcontroller, forexample. One or more of the TEC controller 115 and various modules 111,112, 113, 115 can be implemented in hardware or can be implemented bycomputer readable program code (stored in the memory 120 or anotherlocation) executed by a central processing unit (CPU) of the controller110.

The host interface module 111 receives host commands (e.g., read andwrite commands) through a storage interface, such as eMMC or any of theother interface listed above, for example. The flash management module112 is firmware executed by the controller 110 to handle host requestsand translate them to NAND flash operations, and the flash interfacemodule 113 performs memory operation according to instructions providedby the flash management module 112.

The TEC controller 115 is used in conjunction with the TEC 130 toprovide power to the TEC 130 to heat or cool the NAND memory dies 120,as appropriate. As discussed above, the behavior of memories, such asNAND flash memories, is often very dependent on temperature. In hightemperatures, the endurance is improved due to better annealing, butdata retention is degraded. In very low temperatures, other effects areprominent. Memory designers take this dependence into consideration toproduce a memory that operates in a wide range of temperatures, butusing a wide range of temperatures is often not optimal, as certaincharacteristics are better suited for a smaller temperature rangetailored to their specific operations.

This embodiment can be used to set the temperature of the storage module100 at a temperature best suited for its particular operation. Further,with this embodiment, the end user of the storage module 100 can begiven the ability to control the storage module's temperature toemphasize a desired system or memory (e.g., NAND) characteristic, suchas endurance or data retention. For example, with some memorytechnologies, a temperature range of 0 C to 40 C is preferred for highdata retention, while a temperature range of 55 C to 85 C is preferredfor high endurance.

In operation, the TEC controller 115 compares a temperature reading fromthe temperature sensor 125 to a target temperature. The targettemperature can be provided to the TEC controller 115 by the flashmanagement module 112, and the TEC controller 115 can obtain thetemperature reading from the temperature sensor 125 through a NANDcommand. If the temperature reading from the temperature sensor 125differs from the target temperature, the TEC controller 115 can activatethe TEC 130 to either cool or heat the memory 120, as appropriate. Thisoperation is shown in the flow chart 300 in FIG. 3.

As shown in FIG. 3, the TEC controller 115 compares the temperaturereading from the temperature sensor 125 with a target temperature (act310). The target temperature can be predetermined (fixed) or adjustableby a user of the storage module 100. For example, the user can changethe temperature through a storage protocol command to achieve a desiredmemory characteristic. Also, the target temperature can be a singletemperature (e.g., 55 C) or a temperature range (e.g., 55 C to 85 C). Ifthe temperature reading from the temperature sensor 125 is higher thanthe target temperature, the TEC controller 115 sets the power of the TEC130, so that it cools the memory dies 120 (act 320). If the temperaturereading from the temperature sensor 125 is lower than the targettemperature, the TEC controller 115 sets the power of the TEC 130, sothat it heats the memory dies 120 (act 330). If the temperature readingfrom the temperature sensor 125 is equal to the target temperature, theTEC controller 115 turns off the power of the TEC 130, so that itneither heats nor cools the memory dies 120 (act 340). After waiting aperiod of time (act 350), the method can start over again.

FIG. 4 is a diagram of a circuit of an embodiment for controlling thetemperature. In this example, the target temperature is a range betweenRef 1 (e.g., 55 C) and Ref 2 (e.g., 85 C). As shown in FIG. 4, thiscircuit comprises two op amps 410, 420, a first set of MOSFETs 430, 440on one side of the TEC 130, and a second set of MOSFETs 450, 460 on theother side of the TEC 130. In each pair, only one MOSFET is conductingat a time. In operation, the first op amp 410 compares the temperaturereading from the temperature sensor 125 to the first referencetemperature. If the temperature reading is higher than that referencetemperature, voltage is applied to the first set of MOSFETs 430, 440(430 is conducting) to push current through the TEC 130 to activate acooling operation. The second op amp 420 compares the temperaturereading from the temperature sensor 125 to the second referencetemperature. If the temperature reading is lower than that referencetemperature, voltage is applied to the second set of MOSFETs 450, 460 topull current through the TEC 130 to activate a heating operation. Inthis way, the TEC 130 can maintain a fixed temperature or temperaturerange on the memory dies 120.

There are many configurations and alternatives to these embodiments. Forexample, in the embodiment above, the temperature sensor 125 was part ofthe memory dies 120. However, instead of or in addition to thetemperature sensor 125 in the memory dies 120, the storage module 110can have a temperature sensor 117 in the ASIC of the controller 110 orin another location in the storage module 100 (see FIG. 1). If multipletemperature sensors are used, the TEC controller 115 can use theindividual readings separately (e.g., taking the highest/lowest reading)or use them together in some fashion (e.g., average the readings, applydifferent weights to the readings, etc.).

The TEC 130 can be located in any suitable location in the storagemodule 100, and FIGS. 5-8 illustrate some exemplary configurations. InFIG. 5, the controller 110, memory dies 120, and TEC 130 are all stackedon a substrate 500, with the TEC 130 being located between the substrate500 and the first memory die in the stack of memory dies 120. Thesubstrate 500 is thermally and electrically coupled to a printed circuitboard 510 via a plurality of solder balls 520. The substrate 500 andsolder balls 520 can be part of a ball grid array (BGA) package, such asthe IIL-PBGA package from Intel. FIG. 6 shows the heat transfer from thestorage module 100 of FIG. 5. As can be seen in FIG. 6, although thereis some heat flow from the sides and top of the memory dies 130, most ofthe heat is transferred from the memory dies 120 through the TEC 130 anddissipated through the printed circuit board 510 via the substrate 500and solder balls 520.

If there is a significant temperature gradient between the closest dieto the TEC 130 and the farthest, additional heating/cooling may beneeded, and one or more additional TECs can be added to the storagemodule 100. For example, in FIG. 7, a second TEC 700 is added to the topof the stack, so that the memory dies 120 are sandwiched between the twoTECs 130, 700 so as to isolate the internal dies 120 from the outsidetemperature. As compared to the configuration shown in FIGS. 5 and 6,the controller 110 is moved from the top of the memory dies 120 to thebottom, and a thermally conductive filler 710 is added to fill the void.FIG. 8 shows the heat transfer of this configuration, where the two TECs130, 700 dissipate heat from the top and bottom of the storage module100.

It should be noted that while the TEC(s) were internal to the packaging50 (housing) of the storage module 100 in the above examples, a TECexternal to the packaging 50 (see FIG. 1) can be used instead of or inaddition to the TEC(s) internal to the packaging 50. This alternativemay be preferred in situations where the storage module 100 is beingoperated in an unusually warm or cold environment. Since the externalTEC 150 is located outside of the storage module 100 and not subject tothe space and other constraints, larger devices for cooling or heating(e.g., standard refrigeration techniques) can be used.

In the above example, it was assumed that a target temperature wasdesired for the entire memory die 120 to optimize one NANDcharacteristic. However, there may be more than one NAND characteristicfor which different target temperatures are desired. For example, it maybe desired to design a storage module that has very long data retentionfor user content and very high endurance for a single-level cell (SLC)cache, both of which cannot be optimally achieved at the sametemperature. To address this situation, a memory die can be divided intoa plurality of regions, with each region being associated with adifferent target temperature. The TEC can also be divided into acorresponding plurality of regions that are independently controlled bythe TEC controller. So, for the above example, advantage can be taken ofthe planarity of the TEC and memory to divide the memory and TEC intotwo separate independent units. The first TEC region can heat the cacheblocks and guarantee high endurance, while, at the same time, the secondTEC region can cool the user content blocks (intact blocks) andguarantee high data retention. In this way, a non-uniform temperatureprofile across the TEC is used to achieve different temperatureconditions for different memory uses (here, caching and storage ofintact blocks).

In another embodiment, temperature control of a storage module is usedto prevent the temperature of the memory from rising to levels at orabove the maximum operating temperature rating when a host is sending aburst of data. As used herein, a “burst of data” refers to arelatively-high load period by the host (i.e., a period in which thehost is writing a relatively-high amount of data and/or issues arelatively-high number of write commands). That is, bursts are periodsof time when a higher-than-average performance by the storage module 100is required to satisfy the write activity of the host. In manysituations, the host is operating in a near-idle mode most of the timeand occasionally sends a burst of data when there is a high demand fordata (e.g., when a user activates a host device (such as a camera ormobile phone) or when an email arrives with a large attachment). Thetypical duration of a burst of data is a few seconds, and the requiredperformance is higher than while in other modes. This short andintensive demand for data can increase the temperature of the memory todangerous levels and can negatively affect the system's responsiveness,especially when multiple die parallelism is used to meet increasing readand write performance requirements.

To address this concern, in another embodiment (which can be usedtogether with or separately from the embodiments discussed above, theTEC controller 115 determines that the host is about to send a databurst and then activates the TEC 130 to cool the memory 120 prior to thereceiving of the data burst.

The TEC controller 115 can determiner that the host is about to send adata burst in any suitable manner. For example, the TEC controller 115can receive a notification (e.g., via a storage protocol command) thatthe host is about to send a data burst. This notification can expresslyindicate that a data burst is upcoming or can contain some other messagethat is indicative of an upcoming burst (e.g., that the host buffer isfull). As another example, the storage module 100 can have an internaldetection mechanism for inferring when the burst is about to occur basedon host activity. For example, the storage module 100 can determine ifthe write activity of the host over a time period exceeds a threshold.The write activity can be, for example, an amount of data received fromthe host to be written in the storage module 100 and/or a number ofwrite commands received from the host (e.g., the number of input/outputoperations per second (“IOPS”)). It is preferred that the time periodover which the storage module 100 assesses whether there is a burst ofdata be small enough to enable fast detection of the data burst butlarge enough to eliminate noise in the detection (e.g., 100-200 msec).Additionally, the threshold against which to measure write activity canbe static (an absolute number) (e.g., data being received from the hostat a rate of 40 MB/sec and/or 200-2,000 write commands being receivedfrom the host over a 100-200 msec window) or dynamic (a relative number)(e.g., as a percentage based on previous write activity of the host(over the same or different time period) in a weighted or unweightedmanner). If the storage module 100 is designed to both accept anotification from the host and to have an internal detection mechanism,rules can be set to determine which indication to follow if there is aclash (e.g., the notification from the host would trigger the coolingoperation, and the later indication from the internal detectionmechanism would be ignored).

Irrespective of the method used, when the TEC controller 115 determinesthat the host is about to send the burst, the TEC controller 115activates the TEC 130 to cool the memory 120 prior to the host sendngthe burst. A target low temperature can be set, or the TEC 130 can justrun until turned off. This “pre-cools” the memory 120 to account for theheat to be generated when the host sends the burst. The TEC controller115 can determine when to stop cooling the memory 120 either in responseto a notification from the host or by making an inference from the writeactivity of the host.

FIGS. 9A and 9B illustrate this embodiment. As shown in FIG. 9A, beforeand after the data burst, the host is in an idle mode. As shown in FIGS.9A and 9B, before the host sends the data burst, the memory 120 isoperating at a constant temperature below the maximum operatingtemperature. In the situation where four-die parallelism is used, thetemperature of the memory 120 rises when the host sends a burst of dataand peaks at a temperature of a delta T above the temperature of thenormal operation condition. As shown in FIG. 9B, this peak temperatureis below the maximum operating temperature but is still relatively high.However, when eight-die parallelism is used, a temperature rise of 2×delta T is encounter during the burst, which raises the temperature ofthe memory 120 above the maximum operating temperature and can result indamage to the storage module 100.

Using the method of this embodiment, when the storage module 100receives a burst notification from the host, it begins to cool thememory 120 before burst is received. This lowers the temperature floorof the memory 120, so that even with a temperature rise of 2× delta T,the temperature is lower than the maximum operating temperature.

There are many alternatives that can be used with this embodiment. Forexample, instead of stopping the cooling of the memory at the end of theburst, the TEC controller 115 can provide further cooling after the endof the burst to prepare for the next burst, especially if the next burstwill occur a short time (e.g., 15 seconds) later or when the start ofthe burst is detected internally by the storage device 100 (since theinternal detection may cause the cooling to start after the burst hasstarted). In another alternate embodiment (shown in FIG. 10), instead ofor in addition to the TEC controller 115 in the storage module 100controlling one or more TECs, the host 1025 can contains its own TECcontroller 1040 and one or more of its own TECs 1050 external to thestorage module package 50 (but preferably close to it). As anotheralternative, the controller 30 in the host 1025 can send instructions tothe TEC controller 115 in the storage module 100 (e.g., via storageprotocol commands) to operate the TEC(s) 130, 150 in and around thestorage module 100. Conversely, the TEC controller 115 in the storagemodule 100 can instruct the TEC controller 1040 in the host 1025 tooperate its TEC 1050.

It is intended that the foregoing detailed description be understood asan illustration of selected forms that the invention can take and not asa definition of the invention. It is only the following claims,including all equivalents, that are intended to define the scope of theclaimed invention. Finally, it should be noted that any aspect of any ofthe preferred embodiments described herein can be used alone or incombination with one another.

What is claimed is:
 1. A storage module comprising: a memory; atemperature sensor; a thermoelectric cooler; and a controller incommunication with the memory, the temperature sensor, and thethermoelectric cooler, wherein the controller is configured to: comparea temperature reading from the temperature sensor to a targettemperature; and if the temperature reading differs from the targettemperature, activate the thermoelectric cooler.
 2. The storage moduleof claim 1, wherein the target temperature is predetermined.
 3. Thestorage module of claim 1, wherein the target temperature is adjustableby a user of the storage module.
 4. The storage module of claim 1,wherein the target temperature is a single temperature.
 5. The storagemodule of claim 1, wherein the target temperature is a temperaturerange.
 6. The storage module of claim 1, wherein if the temperaturereading is higher than the target temperature, the controller activatesthe thermoelectric cooler to cool the memory.
 7. The storage module ofclaim 6, wherein if the temperature reading is lower than the targettemperature, the controller activates the thermoelectric cooler to heatthe memory.
 8. The storage module of claim 1, wherein the memorycomprises a memory die and a substrate, and wherein the thermoelectriccooler is located between the memory die and the substrate.
 9. Thestorage module of claim 8 further comprising a printed circuit board anda plurality of solder balls thermally and electrically coupling thesubstrate with the printed circuit board.
 10. The storage module ofclaim 1, wherein the memory comprises a plurality of memory dies,wherein the storage module comprises an additional thermoelectriccooler, and wherein the plurality of memory dies are located between thethermoelectric cooler and the additional thermoelectric cooler.
 11. Thestorage module of claim 1 further comprising packaging housing thecontroller and the memory, and wherein the thermoelectric cooler isinternal to the packaging.
 12. The storage module of claim 1 furthercomprising packaging housing the controller and the memory, and whereinthe thermoelectric cooler is external to the packaging.
 13. The storagemodule of claim 1, wherein the temperature sensor is located in thememory.
 14. The storage module of claim 1, wherein the temperaturesensor is located in the controller.
 15. The storage module of claim 1,wherein the memory is divided into a plurality of regions, eachassociated with a different target temperature, and wherein thethermoelectric cooler is divided into a corresponding plurality ofregions that are independently controlled by the controller.
 16. Thestorage module of claim 1, wherein the storage module is embedded in ahost.
 17. The storage module of claim 1, wherein the storage module isremovably connected to a host.
 18. The storage module of claim 1,wherein the memory is a NAND memory.
 19. The storage module of claim 1,wherein the storage module is a solid-state drive.
 20. A storage modulecomprising: a substrate; a memory die; a thermoelectric cooler locatedbetween the memory die and the substrate; and packaging that houses thesubstrate, memory die, and thermoelectric cooler.
 21. The storage moduleof claim 20 further comprising a second thermoelectric cooler located onan other side of the memory die.
 22. The storage module of claim 21further comprising at least one additional memory die located betweenthe memory die and the second thermoelectric cooler.
 23. The storagemodule of claim 20 further comprising a controller located on an otherside of the memory die.
 24. The storage module of claim 23 furthercomprising at least one additional memory die located between the memorydie and the controller.
 25. The storage module of claim 20 furthercomprising a controller located between the memory die and thethermoelectric cooler.
 26. The storage module of claim 20, wherein thestorage module is embedded in a host.
 27. The storage module of claim20, wherein the storage module is removably connected to a host.
 28. Thestorage module of claim 20, wherein the memory die is a NAND memory die.29. The storage module of claim 20, wherein the storage module is asolid-state drive.
 30. A method of controlling temperature of a storagemodule, the method comprising: performing the following in a memorymodule having a memory, a temperature sensor, and a thermoelectriccooler: comparing a temperature reading from the temperature sensor to atarget temperature; and if the temperature reading differs from thetarget temperature, activating the thermoelectric cooler.
 31. The methodof claim 30, wherein the target temperature is predetermined.
 32. Themethod of claim 30, wherein the target temperature is adjustable by auser of the storage module.
 33. The method of claim 30, wherein thetarget temperature is a single temperature.
 34. The method of claim 30,wherein the target temperature is a temperature range.
 35. The method ofclaim 30, wherein if the temperature reading is higher than the targettemperature, the thermoelectric cooler is activated to cool the memory.36. The method of claim 35, wherein if the temperature reading is lowerthan the target temperature, the thermoelectric cooler is activated toheat the memory.
 37. The method of claim 30, wherein the memorycomprises a memory die and a substrate, and wherein the thermoelectriccooler is located between the memory die and the substrate.
 38. Themethod of claim 37 further comprising a printed circuit board and aplurality of solder balls thermally and electrically coupling thesubstrate with the printed circuit board.
 39. The method of claim 30,wherein the memory comprises a plurality of memory dies, wherein thestorage module comprises an additional thermoelectric cooler, andwherein the plurality of memory dies are located between thethermoelectric cooler and the additional thermoelectric cooler.
 40. Themethod of claim 30, wherein the storage module comprises packaginghousing the controller and the memory, and wherein the thermoelectriccooler is internal to the packaging.
 41. The method of claim 30, whereinthe storage module comprises packaging housing the controller and thememory, and wherein the thermoelectric cooler is external to thepackaging.
 42. The method of claim 30, wherein the temperature sensor islocated in the memory.
 43. The method of claim 30, wherein thetemperature sensor is located in the controller.
 44. The method of claim30, wherein the memory is divided into a plurality of regions, eachassociated with a different target temperature, and wherein thethermoelectric cooler is divided into a corresponding plurality ofregions that are independently controlled by the controller.
 45. Themethod of claim 30, wherein the storage module is embedded in a host.46. The method of claim 30, wherein the storage module is removablyconnected to a host.
 47. The method of claim 30, wherein the memory is aNAND memory.
 48. The method of claim 30, wherein the storage module is asolid-state drive.